Commit 266d4f9e authored by Martin Vítek's avatar Martin Vítek

Working DFLL 48MHz

parent 0770cd0d
......@@ -16,7 +16,7 @@ System::System()
void System::init_clock()
{
//Enable external 32kHz crystal, 1068us start-up
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(0x06) | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K;
SYSCTRL->XOSC32K.reg = SYSCTRL_XOSC32K_STARTUP(0x03) | SYSCTRL_XOSC32K_XTALEN | SYSCTRL_XOSC32K_EN32K;
SYSCTRL->XOSC32K.bit.ENABLE = 1;
while (!SYSCTRL->PCLKSR.bit.XOSC32KRDY) ;;
......@@ -26,7 +26,7 @@ void System::init_clock()
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_XOSC32K | GCLK_GENCTRL_ID(1);
while(GCLK->STATUS.bit.SYNCBUSY) ;;
//Enable reference clock for DFLL
GCLK->CLKCTRL.reg = GCLK_CLKCTRL_CLKEN | GCLK_CLKCTRL_GEN(1) | GCLK_CLKCTRL_ID_DFLL48M;
......@@ -34,20 +34,22 @@ void System::init_clock()
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
SYSCTRL->DFLLCTRL.reg = 0;
//Get and load coarse and fine values from NVM
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
//Get and load coarse and fine values from NVM
SYSCTRL->DFLLVAL.reg = SYSCTRL_DFLLVAL_COARSE((*(uint32_t *) FUSES_DFLL48M_COARSE_CAL_ADDR >> FUSES_DFLL48M_COARSE_CAL_Pos)) |
SYSCTRL_DFLLVAL_FINE( (*(uint32_t *) FUSES_DFLL48M_FINE_CAL_ADDR >> FUSES_DFLL48M_FINE_CAL_Pos));
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
//Set coarse step, fine step, multiplier
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(31) |
SYSCTRL_DFLLMUL_FSTEP(31) |
SYSCTRL->DFLLMUL.reg = SYSCTRL_DFLLMUL_CSTEP(5) |
SYSCTRL_DFLLMUL_FSTEP(10) |
SYSCTRL_DFLLMUL_MUL(48000000/32768);
//Start closed-loop
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_QLDIS | SYSCTRL_DFLLCTRL_MODE;
SYSCTRL->DFLLCTRL.reg = SYSCTRL_DFLLCTRL_QLDIS | SYSCTRL_DFLLCTRL_CCDIS | SYSCTRL_DFLLCTRL_MODE;
//Enable DFLL 48MHz as clock source
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
......@@ -56,12 +58,21 @@ void System::init_clock()
while (!SYSCTRL->PCLKSR.bit.DFLLRDY) ;;
//Set flash wait state to 1, which we need to do at 48MHz
NVMCTRL->CTRLB.bit.RWS = 1;
//Set DFLL as GCLK0 source
GCLK->GENDIV.reg = GCLK_GENDIV_DIV(1) | GCLK_GENDIV_ID(0);
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_IDC | GCLK_GENCTRL_ID(0);
while(GCLK->STATUS.bit.SYNCBUSY) ;;
GCLK->GENCTRL.reg = GCLK_GENCTRL_GENEN | GCLK_GENCTRL_SRC_DFLL48M | GCLK_GENCTRL_IDC | GCLK_GENCTRL_ID(0) | GCLK_GENCTRL_OE;
while(GCLK->STATUS.bit.SYNCBUSY) ;;
PM->CPUSEL.reg = PM_CPUSEL_CPUDIV_DIV1 ;
PM->APBASEL.reg = PM_APBASEL_APBADIV_DIV1_Val ;
PM->APBBSEL.reg = PM_APBBSEL_APBBDIV_DIV1_Val ;
PM->APBCSEL.reg = PM_APBCSEL_APBCDIV_DIV1_Val ;
SystemCoreClock = 48'000'000;
}
......
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