Commit d034d6e8 authored by Martin Vítek's avatar Martin Vítek

Add hiearchical labels for separators

parent 257d6898
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
......
update=Tue 18 Apr 2017 11:54:08 CEST
update=31. 5. 2017 17:23:31
version=1
last_client=kicad
[pcbnew]
......@@ -25,16 +25,6 @@ version=1
[cvpcb]
version=1
NetIExt=net
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceForceRefPrefix=0
SpiceUseNetNumbers=0
LabSize=50
[eeschema]
version=1
LibDir=../HW
......@@ -125,3 +115,13 @@ LibName83=Worldsemi
LibName84=Xicor
LibName85=zetex
LibName86=Zilog
[schematic_editor]
version=1
PageLayoutDescrFile=
PlotDirectoryName=
SubpartIdSeparator=0
SubpartFirstId=65
NetFmtName=
SpiceAjustPassiveValues=0
LabSize=50
ERC_TestSimilarLabels=1
This diff is collapsed.
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
......
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
......
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
......
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A3 16535 11693
encoding utf-8
......@@ -206,65 +206,65 @@ Wire Wire Line
2050 2950 2050 2750
Text GLabel 1600 2550 0 50 Input ~ 0
DIGIT_1
Text HLabel 15350 8900 2 60 Input ~ 0
Text HLabel 15300 8600 2 60 Input ~ 0
DIGIT_1
Wire Wire Line
15350 8900 15250 8900
Text GLabel 15250 8900 0 50 Output ~ 0
15300 8600 15200 8600
Text GLabel 15200 8600 0 50 Output ~ 0
DIGIT_1
Text HLabel 15350 9000 2 60 Input ~ 0
Text HLabel 15300 8700 2 60 Input ~ 0
DIGIT_2
Wire Wire Line
15350 9000 15250 9000
Text GLabel 15250 9000 0 50 Output ~ 0
15300 8700 15200 8700
Text GLabel 15200 8700 0 50 Output ~ 0
DIGIT_2
Text HLabel 15350 9100 2 60 Input ~ 0
Text HLabel 15300 8800 2 60 Input ~ 0
DIGIT_3
Wire Wire Line
15350 9100 15250 9100
Text GLabel 15250 9100 0 50 Output ~ 0
15300 8800 15200 8800
Text GLabel 15200 8800 0 50 Output ~ 0
DIGIT_3
Text HLabel 15350 9200 2 60 Input ~ 0
Text HLabel 15300 8900 2 60 Input ~ 0
DIGIT_4
Wire Wire Line
15350 9200 15250 9200
Text GLabel 15250 9200 0 50 Output ~ 0
15300 8900 15200 8900
Text GLabel 15200 8900 0 50 Output ~ 0
DIGIT_4
Text HLabel 15350 9300 2 60 Input ~ 0
Text HLabel 15300 9000 2 60 Input ~ 0
DIGIT_5
Wire Wire Line
15350 9300 15250 9300
Text GLabel 15250 9300 0 50 Output ~ 0
15300 9000 15200 9000
Text GLabel 15200 9000 0 50 Output ~ 0
DIGIT_5
Text HLabel 15350 9400 2 60 Input ~ 0
Text HLabel 15300 9100 2 60 Input ~ 0
DIGIT_6
Wire Wire Line
15350 9400 15250 9400
Text GLabel 15250 9400 0 50 Output ~ 0
15300 9100 15200 9100
Text GLabel 15200 9100 0 50 Output ~ 0
DIGIT_6
Text HLabel 15350 9500 2 60 Input ~ 0
Text HLabel 15300 9200 2 60 Input ~ 0
NUMBER_A
Wire Wire Line
15350 9500 15250 9500
Text GLabel 15250 9500 0 50 Output ~ 0
15300 9200 15200 9200
Text GLabel 15200 9200 0 50 Output ~ 0
NUMBER_A
Text HLabel 15350 9600 2 60 Input ~ 0
Text HLabel 15300 9300 2 60 Input ~ 0
NUMBER_B
Wire Wire Line
15350 9600 15250 9600
Text GLabel 15250 9600 0 50 Output ~ 0
15300 9300 15200 9300
Text GLabel 15200 9300 0 50 Output ~ 0
NUMBER_B
Text HLabel 15350 9700 2 60 Input ~ 0
Text HLabel 15300 9400 2 60 Input ~ 0
NUMBER_C
Wire Wire Line
15350 9700 15250 9700
Text GLabel 15250 9700 0 50 Output ~ 0
15300 9400 15200 9400
Text GLabel 15200 9400 0 50 Output ~ 0
NUMBER_C
Text HLabel 15350 9800 2 60 Input ~ 0
Text HLabel 15300 9500 2 60 Input ~ 0
NUMBER_D
Wire Wire Line
15350 9800 15250 9800
Text GLabel 15250 9800 0 50 Output ~ 0
15300 9500 15200 9500
Text GLabel 15200 9500 0 50 Output ~ 0
NUMBER_D
$Comp
L 4028 U2
......@@ -2820,4 +2820,16 @@ $EndComp
Wire Wire Line
15750 7250 15750 7100
Connection ~ 15750 6650
Text HLabel 15300 9600 2 50 Input ~ 0
SEPARATOR_1
Text GLabel 15200 9600 0 50 Output ~ 0
SEPARATOR_1
Wire Wire Line
15200 9600 15300 9600
Text HLabel 15300 9700 2 50 Input ~ 0
SEPARATOR_2
Text GLabel 15200 9700 0 50 Output ~ 0
SEPARATOR_2
Wire Wire Line
15200 9700 15300 9700
$EndSCHEMATC
......@@ -86,7 +86,7 @@ LIBS:Xicor
LIBS:zetex
LIBS:Zilog
LIBS:ZCU-nixie-clock-cache
EELAYER 25 0
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
......
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