From 43b39a3358d30643bfef837e0bbfa534090b6c63 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20V=C3=ADtek?= <fotomartinkv@gmail.com> Date: Fri, 8 Jul 2016 15:09:36 +0200 Subject: [PATCH] Add HW files --- HW/gate-servo-controller.brd | 384 ++++++++++++++++++++++++++++++++ HW/gate-servo-controller.sch | 411 +++++++++++++++++++++++++++++++++++ 2 files changed, 795 insertions(+) create mode 100644 HW/gate-servo-controller.brd create mode 100644 HW/gate-servo-controller.sch diff --git a/HW/gate-servo-controller.brd b/HW/gate-servo-controller.brd new file mode 100644 index 0000000..5db0bbd --- /dev/null +++ b/HW/gate-servo-controller.brd @@ -0,0 +1,384 @@ +<?xml version="1.0" encoding="utf-8"?> +<!DOCTYPE eagle SYSTEM "eagle.dtd"> +<eagle version="7.2.0"> +<drawing> +<settings> +<setting alwaysvectorfont="no"/> +<setting verticaltext="up"/> +</settings> +<grid distance="0.05" unitdist="inch" unit="inch" style="lines" multiple="1" display="no" altdistance="0.025" altunitdist="inch" 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Sollte ihre Platine +besondere Anforderungen haben, treffen Sie die erforderlichen +Einstellungen hier und speichern die Design Rules unter +einem neuen Namen ab.</description> +<description language="en"><b>EAGLE Design Rules</b> +<p> +The default Design Rules have been set to cover +a wide range of applications. Your particular design +may have different requirements, so please make the +necessary adjustments and save your customized +design rules under a new name.</description> +<param name="layerSetup" value="(1*16)"/> +<param name="mtCopper" value="0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm 0.035mm"/> +<param name="mtIsolate" value="1.5mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm 0.15mm 0.2mm"/> +<param name="mdWireWire" value="8mil"/> +<param name="mdWirePad" value="8mil"/> +<param name="mdWireVia" value="8mil"/> +<param name="mdPadPad" value="8mil"/> +<param name="mdPadVia" value="8mil"/> +<param name="mdViaVia" value="8mil"/> +<param name="mdSmdPad" value="8mil"/> +<param name="mdSmdVia" value="8mil"/> +<param name="mdSmdSmd" value="8mil"/> +<param name="mdViaViaSameLayer" value="8mil"/> +<param name="mnLayersViaInSmd" value="2"/> +<param name="mdCopperDimension" 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gate="G$1" pin="ADC6" pad="19"/> +<connect gate="G$1" pin="ADC7" pad="22"/> +<connect gate="G$1" pin="AREF" pad="20"/> +<connect gate="G$1" pin="AVCC" pad="18"/> +<connect gate="G$1" pin="GND" pad="21"/> +<connect gate="G$1" pin="GND@1" pad="3"/> +<connect gate="G$1" pin="GND@2" pad="5"/> +<connect gate="G$1" pin="PB0(ICP)" pad="12"/> +<connect gate="G$1" pin="PB1(OC1A)" pad="13"/> +<connect gate="G$1" pin="PB2(SS/OC1B)" pad="14"/> +<connect gate="G$1" pin="PB3(MOSI/OC2)" pad="15"/> +<connect gate="G$1" pin="PB4(MISO)" pad="16"/> +<connect gate="G$1" pin="PB5(SCK)" pad="17"/> +<connect gate="G$1" pin="PB6(XTAL1/TOSC1)" pad="7"/> +<connect gate="G$1" pin="PB7(XTAL2/TOSC2)" pad="8"/> +<connect gate="G$1" pin="PC0(ADC0)" pad="23"/> +<connect gate="G$1" pin="PC1(ADC1)" pad="24"/> +<connect gate="G$1" pin="PC2(ADC2)" pad="25"/> +<connect gate="G$1" pin="PC3(ADC3)" pad="26"/> +<connect gate="G$1" pin="PC4(ADC4/SDA)" pad="27"/> +<connect gate="G$1" pin="PC5(ADC5/SCL)" pad="28"/> +<connect gate="G$1" pin="PC6(/RESET)" pad="29"/> +<connect gate="G$1" pin="PD0(RXD)" pad="30"/> +<connect gate="G$1" pin="PD1(TXD)" pad="31"/> +<connect gate="G$1" pin="PD2(INT0)" pad="32"/> +<connect gate="G$1" pin="PD3(INT1)" pad="1"/> +<connect gate="G$1" pin="PD4(XCK/T0)" pad="2"/> +<connect gate="G$1" pin="PD5(T1)" pad="9"/> +<connect gate="G$1" pin="PD6(AIN0)" pad="10"/> +<connect gate="G$1" pin="PD7(AIN1)" pad="11"/> +<connect gate="G$1" pin="VCC@1" pad="4"/> +<connect gate="G$1" pin="VCC@2" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="ATMEGA88PA-MU" constant="no"/> +<attribute name="OC_FARNELL" value="1715491" constant="no"/> +<attribute name="OC_NEWARK" value="15R0272" constant="no"/> +</technology> +</technologies> +</device> +<device name="-AI" package="TQFP32-08"> +<connects> +<connect gate="G$1" pin="ADC6" pad="19"/> +<connect gate="G$1" pin="ADC7" pad="22"/> +<connect gate="G$1" pin="AREF" pad="20"/> +<connect gate="G$1" pin="AVCC" pad="18"/> +<connect gate="G$1" pin="GND" pad="21"/> +<connect gate="G$1" pin="GND@1" pad="3"/> +<connect gate="G$1" pin="GND@2" pad="5"/> +<connect gate="G$1" pin="PB0(ICP)" pad="12"/> +<connect gate="G$1" pin="PB1(OC1A)" pad="13"/> +<connect gate="G$1" pin="PB2(SS/OC1B)" pad="14"/> +<connect gate="G$1" pin="PB3(MOSI/OC2)" pad="15"/> +<connect gate="G$1" pin="PB4(MISO)" pad="16"/> +<connect gate="G$1" pin="PB5(SCK)" pad="17"/> +<connect gate="G$1" pin="PB6(XTAL1/TOSC1)" pad="7"/> +<connect gate="G$1" pin="PB7(XTAL2/TOSC2)" pad="8"/> +<connect gate="G$1" pin="PC0(ADC0)" pad="23"/> +<connect gate="G$1" pin="PC1(ADC1)" pad="24"/> +<connect gate="G$1" pin="PC2(ADC2)" pad="25"/> +<connect gate="G$1" pin="PC3(ADC3)" pad="26"/> +<connect gate="G$1" pin="PC4(ADC4/SDA)" pad="27"/> +<connect gate="G$1" pin="PC5(ADC5/SCL)" pad="28"/> +<connect gate="G$1" pin="PC6(/RESET)" pad="29"/> +<connect gate="G$1" pin="PD0(RXD)" pad="30"/> +<connect gate="G$1" pin="PD1(TXD)" pad="31"/> +<connect gate="G$1" pin="PD2(INT0)" pad="32"/> +<connect gate="G$1" pin="PD3(INT1)" pad="1"/> +<connect gate="G$1" pin="PD4(XCK/T0)" pad="2"/> +<connect gate="G$1" pin="PD5(T1)" pad="9"/> +<connect gate="G$1" pin="PD6(AIN0)" pad="10"/> +<connect gate="G$1" pin="PD7(AIN1)" pad="11"/> +<connect gate="G$1" pin="VCC@1" pad="4"/> +<connect gate="G$1" pin="VCC@2" pad="6"/> +</connects> +<technologies> +<technology name=""> +<attribute name="MF" value="" constant="no"/> +<attribute name="MPN" value="ATMEGA8-16AU" constant="no"/> +<attribute name="OC_FARNELL" value="9171371" constant="no"/> +<attribute name="OC_NEWARK" value="73M8863" constant="no"/> +</technology> +</technologies> +</device> +</devices> +</deviceset> +</devicesets> +</library> +</libraries> +<attributes> +</attributes> +<variantdefs> +</variantdefs> +<classes> +<class number="0" name="default" width="0" drill="0"> +</class> +</classes> +<parts> +<part name="IC1" library="atmel" deviceset="MEGA8" device="-AI" value="ATmega8A-AI"/> +</parts> +<sheets> +<sheet> +<plain> +</plain> +<instances> +<instance part="IC1" gate="G$1" x="45.72" y="45.72"/> +</instances> +<busses> +</busses> +<nets> +</nets> +</sheet> +</sheets> +</schematic> +</drawing> +</eagle> -- GitLab